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  1. #1
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    how to define chip edge

    Hi, all,

    I'm learning the layout design, when I do the DRC check, I received the error:
    GR999: RX must be within CHIPEDGE>=0.00 um
    GR999: M1 must be within CHIPEDGE>=0.00 um
    GR999a: PC must be within CHIPEDGE>=0.00 um
    GR999a: NW must be within CHIPEDGE>=0.00 um

    It seems that every layer should be inside the chip edge. However, I don't know how to define the chip edge, any one can help me with this?

    •   Alt4th June 2010, 05:47

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  2. #2
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    Re: how to define chip edge

    Perhaps CHIPEDGE is a layer name in your process? Search the LSW for it!


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    •   Alt4th June 2010, 12:14

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    how to define chip edge

    I take it from the errors that you're using an IBM PDK? Insert Image_bevel, set the dimensions of your chip and make the origin (0,0). If you're not in the final stages of your design, you can do Calibre and Assura DRC with the "Cell" switch on so that it doesn't do checks related to CHIPEDGE.


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    •   Alt4th June 2010, 13:10

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    how to define chip edge

    Thank you! Yes, I'm using the IBM PDK, and the problem is solved when I choose the cell switch on. By the way, do you know where I can choose "insert Image_bevel"?


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    Re: how to define chip edge

    it is a layout pcell, you add it like any other instance. there is no schematic view for it though.


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    •   Alt4th June 2010, 15:21

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  6. #6
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    Re: how to define chip edge

    Quote Originally Posted by oermens View Post
    it is a layout pcell, you add it like any other instance. there is no schematic view for it though.
    Thank you~~



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