Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

synopsys vcs vhdl and verilog mix simulation

Status
Not open for further replies.
W

wu8d

Newbie level 1
Joined
Aug 20, 2008
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,290
Does any one know how to do synopsys vcs vhdl and verilog mix simulation?
I cannot find any tutorial or document about that.
so if anybody know
please write the correct document/tutorial name.
I have search the internet for days.
but only discussion, no exact answers.

I know it should support that. But I don't know how to do.
There are command parameter in vcs
Any one give me a successful tutorial?

I'm using the default lib.
the default lsi_10k lib needs mix simulation.

Added after 3 minutes:

Typically when doing post synthesis simulation.
I cannot compile the simulation because it needs lsi_10k lib, which is described by vhdl.
 

About the MIX simulation, you can get more flow from the VCS manual.
1. You should create the *.setup file;
2. You should compile VHDL/Verilog into lib folder such as work
3. Add +vhdllib+work parameters
etc.

You can reference the VCS manual.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top