VHDL - Shift register

Pheetuz said:

Hi folks.

I have been doing a project for uni where i am using shift registers to convert a 4bit number to serial and then back to parallel.

I have written the code below and simulated it, and it seems to work fine, however when i have actually built the circuit it is not functioning at all as expected.

-This is only the first shift register of the pair ... the number being concatinated onto the original signal is essential to the functioning of the second shift register.

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Shift_reg is port (
	bin	: in unsigned(3 downto 0);
	sout	: out std_logic;
	load, clk	: in std_logic );

--		attribute pin_numbers of Shift_reg: entity is
--		"bin(0):2 bin(1):3 bin(2):4 bin(3):5 load:6 sout:19";




end Shift_reg;

architecture reg of Shift_reg is
	
begin
	Right:	process (clk, bin, load)
		variable temp : unsigned (7 downto 0);
		begin
			if rising_edge(clk) then
				if load = '1' then temp := (bin&"1101");
				else temp := temp srl 1;
 			    end if;
			end if;
		sout <= temp(0);
	end process Right;
end reg;

The output is not changing when i apply a clock pulse to the clock input, I think it may have something to do with me not setting temp to a value before i initialise the code but am really not sure.

Any help is greatly appreciated.

/Pete

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