salunkepratik
Newbie level 3
to synchronize and interleave two ADC outputs (under the constraints listed below) to achieve a combined sampling frequency of 160MHz. You will then design a band-pass filter circuit (with a narrow passband) to process your interleaved signal. The processed signal will be sent through the DAC and displayed on the oscilloscope/spectrum analyzer.
Clocking constraints:
1. Single FPGA clock input signal comes from one of the programmable clock inputs (SYSCLK or DSPCLK)
2. A separate DCM/control block is used to control each of the ADCs (see figure below)
3. A third DCM will be used to control the register and circuitry required to combine the ADC data on-chip
Band-pass filter constraints:
1. Clocking frequency of 160MHz
2. Passband center frequency of 67 MHz
3. 3dB down bandwidth of 4 MHz
4. Stop bandwidth of 6 MHz
5. Largest possible center freq range
Clocking constraints:
1. Single FPGA clock input signal comes from one of the programmable clock inputs (SYSCLK or DSPCLK)
2. A separate DCM/control block is used to control each of the ADCs (see figure below)
3. A third DCM will be used to control the register and circuitry required to combine the ADC data on-chip
Band-pass filter constraints:
1. Clocking frequency of 160MHz
2. Passband center frequency of 67 MHz
3. 3dB down bandwidth of 4 MHz
4. Stop bandwidth of 6 MHz
5. Largest possible center freq range