jerry_gzy
Newbie level 1
Hi, I am designing matrix vector computation with xilinx floating point cores.
I am using multiply and accumulate architecture for my design.
the question is, since floating point addition has a following configuration options
- Low latency OR High speed
-DSP48Es No usage OR Full usage
- latency range range 0..11
for Low latency option, it seems that DSP48E is not available (only for High speed option).
for latency range, I notice some data sheet refer the latency =1 being the minimal latency.
so is latency =0 possible? and since high latency(adder) will make accumulate architecture difficult, thus using high latency to speed up clock is not an option, is that ture?
I am using multiply and accumulate architecture for my design.
the question is, since floating point addition has a following configuration options
- Low latency OR High speed
-DSP48Es No usage OR Full usage
- latency range range 0..11
for Low latency option, it seems that DSP48E is not available (only for High speed option).
for latency range, I notice some data sheet refer the latency =1 being the minimal latency.
so is latency =0 possible? and since high latency(adder) will make accumulate architecture difficult, thus using high latency to speed up clock is not an option, is that ture?
