which tool can generate a sdc file

Hi,
I am totally new to soc encounter.
I finish synthesis in Design Compiler,
Now I am using soc encounter to do the place and routing of my design.
When I import the design, a sdc file is needed.

Could anyone tell me which tool generate this file?

Thank you.

The Design Compiler and PrimeTime both can write out the SDC file using write_sdc command, and the PrimeTime is usually prefered.

There is no tool, which can generate sdc. You as a designer need to provide the constraints to do PnR or synthesis.

You need at least one SDC file for your design that's designer created that defines the clock pins and clock waveforms. From there you can use a tool like Design Compiler to write out an incremental SDC file. In Design Compiler, use the read_sdc file to read in your SDC file for your design. Then use the write_sdc command to write out an incremental SDC based on your design. Then in Encounter read in your SDC file with the loadTimingCon command.

sdf file can be generated by PT!

The sdf files can be generated by either PT or DC. But, before writing the sdc file, you need to set all the constraints. The generated sdc file will contain only the constraints what you've set before writing the sdc file.

Again, ideally the designer should write the sdc file. If the designer more worried about the syntax, he can use the tools to write the sdc's.

Design Compiler generates SDC files (Synopsys Design Constraints)

It is clear from the replies here that many of you have not done a real chip design. You do need a "seed" sdc file which defines clocks and input/output delays for the synthesizer. It should also have false paths, multicycle paths, and generated clocks. After synthesis you generate a NEW sdc from DC, you get many new paths generated, lots of nets. You run Primetime on this netlist and read in that sdc. After all the false timing paths have been analyzed and constraints are updated, you write a new sdc which is given to PnR. Primetime is run several times: post-synth, after FloorPlanning & Global PnR, after CTS & Detailed Route, and after Parasitic extraction.

Rajat Sewal

I agree with Rajat on the threads . . . however, Back-End teams are so isolated from Front-End teams, that each team does on understand the original source of the files. I don't attribute it to lack of knowledge, but lack of awareness (and thereby lack of concern). At the end of the day, everything is "created" and nothing is written by any tool . . . but depends on which stage of the process you are. A block-Level SDC is written by designer. But after full chip integration and synthesis, the top-level SDC can be written out by DC or RC

Back-End Team source files:
- Netlist (from DC/RC),
- Top-Level SDC (from DC/RC)
- Floorplan (you create it)
- UPF/CPF (manually written or written out by DC/RC)
- Library Views (from Vendor)

Front-End Team source files
- RTL (from designer)
- Block Level - SDC (from designer/integration engineer)
- CPF/UPF (from designer/architect)

-- adam