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Why clock tree synthesis? Why clock routing?

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sowmya005

sowmya005

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Hi friends,
We know Clock is not synthesized at synthesis, but only after placement.
I want to know why clock needs to be synthesized separately?
In addition to this, before signal routing is done, clock is routed. why?
even high fanout nets are also routed before any other nets. why?

Any detailed explanation is appreciated.
Thanks,
Sowmya
 

Hi,
Both signals are from nature sensitive_needs clear tree structures, also you must route that before others...
By Clocks extra, you must check (eventually) for the delay times/uniformity too & these isnt a simple task, most easy to do as before other nets are routed. :)
Often you need impedance controlled lines too_how do you wish to realise it with an unregular structure?
K.
 

After placement of standard cells, your register and other clocking cells will be fixed.Now the clock tree can be build in order to reduce the cap and trans rules.

Clock tree is routed ahead of signal routing due to the fact that router can utilize low resistance metal paths (top metal layer) so that one can meet the clock max delay requirements easily.

It is not mandatory to route the clock nets a head of signal routing, you can do at the same time.

HFN nets are synthesized but they will be routed along with the other nets in general flows. I think in special case it can be done ahead of signal routing coz they offer uniform structures.
 

Why clock synthesis and clock routing? Because if the clock is not implemented correctly and clock constraints are not met then the design will not work!

It's common to do this after placement, before other timing optimizations and routing as the tool has the best possible conditions to try a meet the constraints it has for clock tree with the available floorplan and placement! If you do not have a good skew/latency/insertion delay at this step for sure you will not meet these conditions if you optimize/route clock together with the other signals!
 
If the output of one register changes on the same clock edge as the input to another register is sampled, it is imperative that change on the first register not have time to reach the second before the clock gets there. Signals other than clocks can generally arrive at different destinations at different times, provided that every destination receives the signal "soon enough". Clocks, however, must arrive simultaneously at all interconnected registers that depend upon them and switch on the same edge.
 

Heyy supercat,
"Action on the same edge" isnt = with the absolute same time in nsec! :)
It means "only", that changes are to find at (some) rise/fall edges, even if Input was related/referenced to + or rising edge, than have you the outgoing pulse changes to same sort of edge to reference, in that case to rising edge of the reference pulse...
Of course; between both "same" rising edges can be lot of time to measure...
K.
 

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