how to reduce mismatch of latch comparator?

Hi,

I've been designing a class-ab latch comparator. This comparator hast to compare a minimal differential input signals of 1mV with the speed of at least 100 MHz. The common problems occurring with latch comparators like offset-voltage, kickback-noise and so on... are not a problem.

Unfortunately after doing a mismatch Monte-Carlo-Sim only 10% work correctly. It seems that the latch is very sensitive. So I increased the transistor-length of the most critical tranisistor-pair in my circuit to reduce the relative error of mismatch. But otherwise increasing the length leads to a time-problem. This means the simulation fails now due to the high frequency. Ok, I tried to reduce the load-capacitance to become more comfortable with the time... but I have still a low yield.

I hope that you could see my problem in reaching a high yield, which is absolutely necessary for me. It's quite frustrating.

Someone an idea that helps?

Thanks

Parallel processing by doubling the hardware (2*50MHz)?

I've found a good solution for my problem: I couldn't expect that I can totally decrease the mismatch-effect. But that's not necessary. The mismatch by the layout or whatever leads to an Input-Offset which I'm cancelling now by an additional external circuit. The decision-threshold is just shifted.

It's clear now, that every iteration of a monte-carlo-sim means just an individual offset for each comparator. So I've to ensure to compensate the offset and then everything is fine.


sorry for the confusion.

Sure: If you can cancel the individual offset, that's the best solution!

Cluny said:

I've found a good solution for my problem: I couldn't expect that I can totally decrease the mismatch-effect. But that's not necessary. The mismatch by the layout or whatever leads to an Input-Offset which I'm cancelling now by an additional external circuit. The decision-threshold is just shifted.

Click to expand...

What is causing the mismatch - capacitance? resistance? or something else?

There are software tools that enable a very precise parasitic extraction, analysis, and eventually extermination (or at least minimization) of a systematic mismatch caused by differences in layouts. Thus, the need for trimming or for offset cancellation circuitry may be eliminated.

Max
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Since I have a lot of comparators working together on one chip, this method seems to be very comfortable. Furthermore it's rather a cancellation algorithm than an additional circuitry.

You could also put a gain stage before it to reduce kickback noise etc.

I have seen some folks put capacitive trim on their inputs to reduce offset.