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The phase shifter design

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xxf_86

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hello everybody,
Can somebody told me the basic theory of clock phase shifter? I want to design one and make the 2MHz clock out to 8 phase signal.
 

I think at such a frequency you could start with a quadruple master clock (ck4 = 8MHz), divide by 2 (ck2), again by2 (ck1), and then feed clk(4,2,1) into an 3:8 decoder.

For higher frequencies, you might like to read this lengthy FPGA thread first.
 

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