DFT Scan - Tetramax - gate off clock in STIL file

All,

In my design I have a multi-cycle path that cannot be captured in a single capture cycle. Hence, I want to extend the time before a capture is made.

Currently, I am considering inserting 5 dead (unused) cycles into the capture routine. Only when these dead cycles are complete do I do an actual capture cycle. The main clock into the design, which s also the scan clock, is free running.

Question:
Does anyone have the code for this, i.e. holding off the capture pulse for 5 dead cycles?

Alternatively,
Perhaps, I could gate off the clock into the design at the start of the capture routine for 5 cycles. Only when this time is complete, I re-instate the clock and the next pulse is the capture pulse.

Question:
Is there a way of temporarily gating off the clock using the STIL file?

Regards,
animotion

You cant reliably use a free running clock for DFT. Scan and most tests need to have the test clock supplied from an input pin so that it can be controlled.

Some people use the free running clock to apply at-speed test vectors. They add hardware that allows a limited number of high speed clock pulses to be applied by the free running clock.

Is your multi-cycle path have too much delay for a single cycle? Or does it have a number of state elements that require clock pulses for the test to propagate?