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Really simple question: Register behavior

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capitan

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Hello,

I'm stumbling on this register behavior on my project.
**broken link removed**

The code for the register is this

Code: 
architecture Behavioral of regn is

begin

process(Clk)
begin
if(Clk'EVENT and Clk='1' and WrEn='1') then
	Q<=D;
end if;
end process;


end Behavioral;

The rising clock edge is right on the transition from 0 to 3 on the d signal. I'm using xilinx 11.5 webpack with ISim. Is this normal? I was expecting 3 to be passed to q right where 7 is and 7 to be passed to q on the next cycle...
 

Hi,

You did not show your testbench code, so I do not know what/how creates wren. When wren is created by the same clock signal, the shown behaviour is incorrect.

The shown behaviour can only occur when wren is active before the rising edge of the clock or becomes active in a delta cycle before the delta cycle of the clock.
Devas
 

Actually this is a very small part of a much bigger circuit implementing the tomasulo algorithm. Wren is created by an fsm (driven by the same common clock as everything really) and some logic so I expect it to come a little after the rising clock edge. Does behavioral simulation take into account gate lags as well? I thought it didn't. I also thought that a register would always insert a 1 cycle lag to propagate d to q.
 

Use a gated clock and try running th simulation.Just make the following changes and see the result:

Code: 
architecture Behavioral of regn is 
signal gClk : std_logic :='0'; 
begin 

gClk <= clk and  WrEn;
process(gClk) 
begin 
if(gClk'EVENT and gClk='1' ) then 
   Q<=D; 
end if; 
end process; 

end Behavioral;
 

    C

    capitan

    Points: 2
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Still I get a problem. D propagates to Q instantly. Is there a way to ALWAYS make sure that a register propagates d to q with a delay of 1 cycle? Why does it propagate instantly?
E.g:
WrEn is always '1'
D changes every rising clock edge
I want D to propagate to Q the next cycle. If WrEn ever falls to 0, Q retains value.
 

By itself, the register does not produce a 1-cycle delay.

The 1-cycle delay is the delay between the generation (not the inspection) of D from the previous edge and the new edge - yielding a change in the Q output one cycle after the D input was changed.

With two registers using the same clock, one feeding the other, you can see the one cycle delay. The first register will transfer the input immediately to its output, and then the second register will change its output to match, one cycle later.
 

    C

    capitan

    Points: 2
    Helpful Answer Positive Rating
I thought you wanted the D to propagate to Q instantly.That is why I suggested yo use gated clock.

For creating a delay, you can try what 'tkbits' has suggested.

--vipin
https://vhdlguru.blogspot.com/
 

it appears I was confused regarding the registers. Thanks everyone
 

Again I am witnessing a very strange and VERY annoying flip flop behavior...Take a look at the diagram and tell me how is that behavior even remotely possible under ANY circumstances

**broken link removed**

I am using the gated clock flip flop vipinlal suggested. Note that if I change the flip flop to what I previously used, flip flop behavior changes yet again. I cannot finish my design if flip flop behavior changes randomly
 

Hi,

In your first post you say that you use ISIM as simulator. I do not have experience with this simulator. I would suggest to download the free Modelsim-XE from the Xilinx website and simulate your design with this simulator.
I would not expect, but maybe the ISIM simulator is not as good as it should be and results in such strange behaviour.
When you get the same behaviour with Modelsim you have really design issues.

Devas
 

I tried using modelsim XE but couldn't get it to work. In compilation, it says that starter version doesn't support 2 HDLs. I use VHDL but I think an ipcore I use from coregen is written in verilog, so I'm stuck with Isim for now. Luckily I have managed to overcome the last flip flop problem. I think chains of flip flops are created even though they are in different components. Anyway thanks for your patience.
 

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