Unexplainable DRC clearance errors

I am getting clearance DRC errors on a part in layout (a 68pin package), some of which are independent of my routing (the vias in the package design are too close apparently), as shown in the image below. I am also getting routing clearance errors.

The reason why this is unexplainable as far as I know is because I am using this exact part from a previous DRC-free design, and I am using the same DRC rules file that the other design had. So it makes no sense to me that mine would show DRC errors while the original doesn't. Also, the routing wires are 0.008in in width, the same wire width used for routing this part in the previous design, yet I am getting clearance issues here too.

Can anyone help? I am baffled, and I have asked a few designers and they are completely clueless as well. Is there some setting that may have changed that I am unaware of (the DRC settings are identical)?

Firstly, are you sure you are using the same drc as the old board?

Could you post the layout file and drc file for two occasions you have used the part - this time and a successful time?

Keith

Hi, yes it is the same DRC file used for both layouts. Here are the contents of that .dru (it's for a 6-layer board):

layerSetup = (1+2*3+4*5+16)
mtCopper = 0.0178mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.0356mm
mtIsolate = 6mil 13mil 7.5mil 13mil 6mil 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 10mil
mdWirePad = 6mil
mdWireVia = 10mil
mdPadPad = 10mil
mdPadVia = 10mil
mdViaVia = 10mil
mdSmdPad = 8mil
mdSmdVia = 8mil
mdSmdSmd = 8mil
mdViaViaSameLayer = 8mil
mnLayersViaInSmd = 2
mdCopperDimension = 40mil
mdDrill = 10mil
mdSmdStop = 0mil
msWidth = 8mil
msDrill = 25mil
msMicroVia = 9.99mm
msBlindViaRatio = 0.500000
rvPadTop = 0.250000
rvPadInner = 0.250000
rvPadBottom = 0.250000
rvViaOuter = 0.250000
rvViaInner = 0.250000
rvMicroViaOuter = 0.250000
rvMicroViaInner = 0.250000
rlMinPadTop = 8mil
rlMaxPadTop = 20mil
rlMinPadInner = 10mil
rlMaxPadInner = 20mil
rlMinPadBottom = 8mil
rlMaxPadBottom = 20mil
rlMinViaOuter = 8mil
rlMaxViaOuter = 20mil
rlMinViaInner = 8mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 4mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 4mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 1.000000
mvCreamFrame = 0.000000
mlMinStopFrame = 0mil
mlMaxStopFrame = 2mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 0mil
srRoundness = 0.000000
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalGap = 0.500000
slMinThermalGap = 25mil
slMaxThermalGap = 100mil
slAnnulusIsolate = 30mil
slThermalIsolate = 10mil
slAnnulusRestring = 0
slThermalRestring = 1
slThermalsForVias = 0
checkGrid = 0
checkAngle = 0
checkFont = 1
checkRestrict = 1
useDiameter = 13
maxErrors = 50

Could you post the .brd file and .dru file so I can load them up in Eagle? You can send them be private message if you prefer.

Keith

Try chnaging the grid and then route again preferably do gridless routing.
I have not worlked on eagle (If the s/w you are using is eagle as per kieth's comment) so dont know if it has an option of gridless routing and If it doesnot have, try minimising the grid as much as possible.This error may be due to the reason that tracks are not exactly in the centre.

Hope this helps you.

Ricky

I felt sure it said Eagle somewhere! Maybe I'm wrong (although the screenshot looks like Eagle).

The drc errors are far too large to be grid errors. Also, there are small errors to adjacent pads where the wires connect to pads implying quite a large design rule. It would be easier to track down with the board layout as I cannot dimension the screenshot.

Keith

Right Keith,

Having a look at PCB will give a better Idea, but I thought if DRC's for both the board are same than grided routing might be a reason.
Also the errors are shown at some places only, means only at 3-4 vias and 3-4 track to via, so from that I thought it has issue with grided routing.

Ricky

I did change the grid values a few times during routing/placing parts. However, that would not explain the DRC errors that involve only the vias of the package (the errors that are independent of routing), right?

Thanks.

I think I have found the problem. NET CLASSES.

Type CLASS and look at the clearance for "power" - it is 12mil. Do the same on the other board and it is 10mil. That over-rides the DRC. I didn't think of it earlier because I rarely use net classes.

Keith.

That fixed the majority of the errors. Thanks.

Still have the routing clearance errors remaining. I'm already using minimum wire width (0.008 in) so I assume they are not centered correctly because of some grid issue.

Appreciate the help guys.

t's not a grid problem. It seems to be the same CLASS problem. Just change the power class clearance to 0 - it fixes the problem. I must admit I am still a little puzzled because the net class for the problem tracks is zero which is the default class, not power. It may be that the pads are defined as power in the library, I am not sure (assuming you can actually define pads as power).


Keith.

Thank you so much. Problem solved.

I never messed with net classes...I guess the designer of the first board may have changed some settings.

I am sure they are useful, so you can specify nets which need to be wider or require more clearance. However, as I design my own circuits and lay out my own boards I rarely use them.

Keith.