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What are the low power RTL techniques for simple microprocessor?

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vivek_p

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Can anyone suggest some implementable low power RTL techniques for a simple microprocessor datapath
 

Re: Low power techniques

in fact, low power verification flow is more complicated!
 

Low power techniques

refer "Practical Low Power VLSI Design" by Gary Yeap.

Its a nice book and he discussed various methods in that book.
 

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    vivek_p

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Re: Low power techniques

Maybe you can try to use Clock Gating.
 

Low power techniques

Clock gating is the way to go with power reduction in RTL... but remember the clock gating cell will also consume power.. There is a trade off between how many flops u want to gate..

PS: These clock gates will come early in the clock tree.. so u need to account of that skew in designing the enable path logic..
 

Low power techniques

There are so many methods!.

* Clock Gating
* Power Shut-Off
* Multi-Vt Cells
* Bus-Invert Encoding.
 

Re: Low power techniques

skyismylimit said:
PS: These clock gates will come early in the clock tree.. so u need to account of that skew in designing the enable path logic..
Click to expand...
Could you please explain in a more detailed way? Maybe an example is better, especially for the skew issue. Thanks.
 

Re: Low power techniques

Can anyone describe the steps/commands to do clock gating using Synopsys Design Compiler

I am new to Synopsys....it will be better if anyone can post the script....and a simple explanation
 

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