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Perhaps you should try using matlab. You can build the math model. I think that there is a possiblity to transfer the math model in VHDL with Matlab. Of Course you need a certain knowledge of Matlab.
Phew. Thanks EJ, but I don't think I have all the required tools to complete that and probably not all the knowledge
I have an embedded soft risk cpu in the fpga, but I had earlier believed that doing it in software would take too long. I just wrote the routine in C and it compiled down to 60 clock cycles which will be about 1uS which is way less than I thought.
I'd still prefer to do it in VHDL, but at least I have a solution if pressed.
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