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Warning : Inferring latches for signal or varialbe

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gokulfun

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Hi all,

Am new to VHDL and this forum.
When executing my VHDL code am getting following warning "Inferring latches for signal or variable "datain_mem" which holds its previous value in one or more paths"
"Inferring latches for signal or variable "datain_reg" which holds its previous value in one or more paths"

my code is
[/code]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity datapath is
port( reset, clk, start: in std_logic;
mainout: out std_logic_vector( 7 downto 0 )
);
end datapath;

architecture struct of datapath is
component controller is
port( clock,GO,rst: in std_logic;
wr,memdrive,aludrive,ld_x,ld_y: out std_logic;
funct_in:in std_logic_vector(7 downto 0);
addr: out std_logic_vector(7 downto 0);
funct: out std_logic_vector(2 downto 0)
);
end component;
component memory is
port ( clock,rst,wr,memdrive : in std_logic;
data_in,address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
component alu is
port( reset, clk, l_x,l_y,aludrive: in std_logic;
xm,ym: in std_logic_vector( 7 downto 0 );
func_m: in std_logic_vector( 2 downto 0);
aluout: out std_logic_vector( 7 downto 0 )
);
end component;
signal address: std_logic_vector( 7 downto 0 );
signal wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s: std_logic;
signal funct_s: std_logic_vector(2 downto 0);
signal mainbus : std_logic_vector( 7 downto 0 );
signal datain_mem ,datain_reg: std_logic_vector( 7 downto 0 );
signal dataout_m,math_out,dataxout,datayout : std_logic_vector( 7 downto 0 );
begin

Control:controller port map(clk,start,reset,wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s,mainbus,address,funct_s);
Mem: memory port map( clk,reset,wr_s,memdrive_s,datain_mem,address,dataout_m);
Arithlogic: alu port map( reset,clk,ld_x_s,ld_y_s,aludrive_s,datain_reg,datain_mem,funct_s,math_out);
mainout <= math_out;
process(clk,wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s,mainbus,dataout_m,math_out)
begin
if (wr_s = '1') then
datain_mem <= mainbus ;
end if;
if (memdrive_s='1' ) then
if (wr_s = '0') then
mainbus <= dataout_m;
else
mainbus<=(others=>'Z');
end if;
if (ld_x_s='1' or ld_y_s='1') then
datain_reg <= mainbus;
end if;
elsif(aludrive_s = '1') then
mainbus <= math_out;
else
mainbus<=(others=>'Z');
end if;
end process;
end struct;

Can anyone pls help me resolve this issue....
Thanks in advance
 

A latch will be inferred only when there is any necessity for storing the state. For eg,
In your code, the value of Datain_mem will be updated only when Wr_s = '1'. When the condition is zero, then there is nothing to do and hence a storage becomes necessary to store the previous value. So a latch in inferred in your design. Just don't leave the default case if it's an IF statement or a CASE statement. Use else statement here to solve your problem. Latches are easily to code but gives tonnes of problems like if you are to do various decisions based on this latched output....

Change your code to something like

if (wr_s = '1') then
datain_mem <= mainbus ;
else
datain_mem <= smallbus;
end if;

Using an else statement in this case should prevent you from infering....Hope you got the point....
Regards
 

Hi all,

Thanks for ur answer. its works.
i got some warning like Tri state node(s) do not directly drive top-level pins

Is this warning matters or not... coz when trying to generate functional simulation netlist, am not getting the wave from file.

Can anyone pls help me to resolve this issue...

Thanks in advance.....
 

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