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How to generate a physical layout of a synthesised VHDL file

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anandkris84

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I have a synthesised vhdl file with TSMC 180 nm library using Synopsys Design Vision.
Now,I want to have the schematic using Cadence Virtuoso.How to do that ?
 

Re: How to generate a physical layout of a synthesised VHDL

yes, it is possible to generate the schematics , but this method is a dirty fix.

Calibre tool(from mentor) will have an utility call ver2lvs . it will convert verilog to lvs netlist or cdl. now you can readin / import this cdl into cadence virtuoso editor to get schematics.

once serious drawback is your schematic will look really ugly. all the transistors will be thrown into different directions.

-Nav
 

Re: How to generate a physical layout of a synthesised VHDL

Yeah I used a place and route tool(Cadence Encounter) and then got the layout in virtuoso
 

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