sweesw
Member level 2
liberty db
If you take a close look at what is contained in your synthesis library, you will definitely find db format library files, but sometimes you can also find .lib filles, those are liberty file format which is used by library compiler to generate those db files. If you read the SOLD document, you will know that the library compiler can generate VHDL files to represent the library as well.
But how can those verilog files that is used to do gate level simulation/verification come from?
Are those files handcrafted by the library designers or can be automatically generated from the liberty files?
I was told that the verilog files and written first and then converted(not automatically) to the liberty files. But I dont believe it, anyone knows the truth?
Please shed some light on it!
If you take a close look at what is contained in your synthesis library, you will definitely find db format library files, but sometimes you can also find .lib filles, those are liberty file format which is used by library compiler to generate those db files. If you read the SOLD document, you will know that the library compiler can generate VHDL files to represent the library as well.
But how can those verilog files that is used to do gate level simulation/verification come from?
Are those files handcrafted by the library designers or can be automatically generated from the liberty files?
I was told that the verilog files and written first and then converted(not automatically) to the liberty files. But I dont believe it, anyone knows the truth?
Please shed some light on it!