alelex
Newbie level 2
Hello guys . I am pretty new to VHDL/Xilinix . I need a project about an atm banking machine implemented on a FPGA , or at least some help . I will be very grateful. Thaks
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type state_type is (st1_Idel, st2_EnterPass, st3_GetRequest, ProcessRequest);
signal state, next_state : state_type;
--Declare internal signals for all outputs of the state-machine
signal Enable_Motor_sig : std_logic;
signal Enable_Motor2_sig : std_logic;
--other outputs
SYNC_PROC: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
state <= st1_Idel;
Enable_Motor_sig <= '0';
else
state <= next_state;
Enable_Motor_out <= Enable_Motor_sig;
-- assign other outputs to internal signals
end if;
end if;
end process;
--MEALY State-Machine - Outputs based on state and inputs
OUTPUT_DECODE: process (state, in1_10dollars, in2_100dollars, ...)
begin
--insert statements to decode internal output signals
--below is simple example
if (state = st4_ProcessRequest and in1_10dollars = '1') then
Enable_Motor1_sig <= '1';
elsif (state = st4_ProcessRequest and in1_100dollars = '1') then
Enable_Motor2_sig <= '1';
else
.....
end if;
end process;
NEXT_STATE_DECODE: process (state,in1_10dollars, in2_100dollars, ...)
begin
case (state) is
when st1_Idel =>
if btn_Enter = '1' then
next_state <= st2_EnterPass;
end if;
when st2_EnterPass =>
if in1_10dollars = '1' then
next_state <= st4_ProcessRequest;
end if;
when .... =>
next_state <= ....;
when others =>
next_state <= ....;
end case;
end process;