Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

help needed: Warning regarding CARRY_SUM

Status
Not open for further replies.
C

cdcll

Full Member level 3
Joined
Feb 15, 2002
Messages
163
Helped
8
Reputation
16
Reaction score
1
Trophy points
1,298
Activity points
1,199
I got warnings as follow(Qu@rtus), I would like to know if and how these warnings will affect my design, and how to correct them? or maybe I can ignore them?

1. Warning: Ignored 13 CARRY_SUM primitives
2. Warning: Ignored 2 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell
3. Warning: Can't place logic feeding CARRY_SUM primitive 74163:2|f74163:sub|140~0 in single logic cell
4. Warning: Ignored 2 CARRY_SUM primitives -- logic cell requires more inputs than it can contain

Thanks in advance.
 

Hi,
Check maximum fanout constraints.
BRMadhukar
 

Thank you for your quick reply.
I am not so clear with constraints,I use all the defaults,could you tell me if I can modify the maximum fanout constraints setting freely? and how to set timing constraints?
 

Hi,
I work on xilinx mostly, but from your problem I realized it may be fanout. In Xilinx there is a User constraint file where all the constraints are define. I shall try for altera and if possible I shall PM you tomorrow.
meanwhile you may find it in max plus documentation.
BRMadhukar
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top