Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

simulation after place and route in ISE 5.2

Status
Not open for further replies.
T

Tomby

Junior Member level 2
Joined
Aug 29, 2003
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
262
compexlib

Hello,

I am trying to run my testbench to do a simulation check after Xilinx has done place and route for the design. When it brings modelsim up and tries to simulate it gives errors such as:

# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)

Can anyone tell me what this error means or what option I need to set in ISE 5.2 to fix this?

Thanks.
 

The simulation libraries for verilog aren't compiled by default, you will have to do it yourself. Check the documentation/help for Compexlib.

Git
 

yes, but it seems to hang and not stop when i run the compxlib

also, since xilinx ise 5.1 generates a new .v file for every step does that mean I have to create a new testbench for the new *.v file that ise generated for the post layout simulation?

Thanks
 

have u added the testbench in your project?? if you added ur testbench, it should not having this problem.. if it still having this problem, look into ur xilinx ISE folder and find simulation library
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top