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VHDL code accepted 1 input and gives 2 different outputs

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aahmadd

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Hi,
I'm trying to write a code in VHDL that accepts 1 input ,other that the (clk and rst), and gives 2 different outputs.
e.g.
input is 11

outputs
a/ 0110
b/ 0011
in order. So if the first output was 0110 then second output will be 0011 and keeps going like that, never 2 same successive outputs, as long as the circuit is running.

Please help me.


Thanks in advance.
 

Re: Help With VHDL

What you're describing is a "finite state machine":

A general model of a Finite State Machine (FSM) consists of both the combinational Logic and sequential components such as state registers, which record the states of circuit and are updated synchronously on the rising edge of the clock signal. The output function computes the various outputs according to different states.
Click to expand...

It sounds like you need a good VHDL text to reference:

Circuit Design with VHDL - Great book reasonably priced

If you do a search for VHDL state machines you see plenty of tutorials and examples.



That should get you going in the right direction.
 

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