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  1. #1
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    Nanosim - State Comparison Errors

    I am a student, working on Digital IC design. When I used Nanosim for Post-Layout simulation, it generates a lot of state comparison errors.

    The inputs to Nanosim are
    1. hspiceD netlist generated from Cadence Virtuoso extracted view from Layout.
    2. Vector file generated from VCD file (obtained by NCVerilog simulation of the verilog gate-level netlist and the SDF file generated by SOC Encounter).
    3. Configuration file.

    The Virtuoso extracted view and Encounter gate-level netlist are checked for LVS and found to be the same.

    Why does this State-comparison error occur, when the input files are the same. How should I go about to solve this error?

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  2. #2
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    Re: Nanosim - State Comparison Errors

    do you have load sim lib ?



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  3. #3
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    Re: Nanosim - State Comparison Errors

    Quote Originally Posted by ljxpjpjljx
    do you have load sim lib ?
    I am not sure, what you are referring to as "sim lib", but let me know, whether the below explanation answers your query.

    1. The gate-level netlist, along with the Verilog library files (obtained from foundry) are used as input to NCVerilog simulation.
    2. The spice model files (obtained from foundry) are also included in the SPICE netlist for Nanosim simulation.

    Is there anything else, you are referring to as "sim lib"?



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