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VHDL language is the same for both of them.
1) Perhaps the question should be which constructions are supported by the synthesis tool I use, which can limit my coding style. Or...
2)do I prefer very behavioral coding versus low level structural coding: in first case code can be portable but, in last case, if you make calls to library components sure code is not portable.
3) If you use "hard" FPGA components like memories, PLLs, multipliers... or similar specific libraries, this part of code is not "portable" in the sense you are calling components that will not exist in the other technology. So, if you instance specific components, code is not portable, but if you can avoid use them (infering memories, multipliers... in the cases where designs permits it, of course) code will be more portable, but also less fast, of course.
I think this question may have some relationship to the difference between ASIC and FPGA. for example in FPGA coding you can call FPGA macro module and in asic you can call designware.
another example is when you writing interface for memory, the timing is different in two conditions.
read the manual of ur particular fpga, focus on the special structures in it.
pay attention to ur coding whenever u're trying to use some kinda structures which can be implemented by tese special structures in fpga.
pay attention to ur memory instantiation.
nothing more.
The main differents between ASIC and FPGA is that :
FPGA is semi-custom. It is base LUT (LUT is small sysem which can execute all basic logic funtions. When you design system in FPGA you can waste much resource (LUT) than is necessary.
ASIC is full-custom. You have to optimize your design before deliver design to fabrication. It take much time to complete ASIC design than FPGA design
For this reason, we can consider ASIC = FPGA is optimized
Coding for every FPGA architecture should be individually thought out in order to fit the structure of logic elements, flip-flops and routing available in that FPGA. Of course, you can just write generic HDL without any consideration for the above, but the quality of results will be drastically poorer. FPGA's are a lot more sensitive to coding style due to comparatively low amount of "building blocks" available to synthesis in comparison to ASIC (lut, FF, routing versus. 2,3,4,6 input AND,OR,XOR,MUX, full adder, half adder, multiple types of flops etc. available in ASIC libraries).
Wow,
ASCI vs FPGA this is really a debatable topic, if cost involved and the volume of production os not an issue.
In FPGA you need not really worry about your timing and layout, theat the work of the Synthesis tool. Alsopower relted heating problems (hot spots) and all is not a major concern.
So for prototyping and testing purposes you prefer FPGA...focus is on getting things to work.
But once the FPGA prototyping is done and the production moves into Mass Production you need to start worrying about the layout of the IC so there are many algos for the same. then you have too many testing phases such as STA (static timing analysis) where the functionality is not tested onlt the design is tested for the desired clocks. There are a lot many other terms associated with the same...
Thats all, more info can be got from the great search engine thats Google
I agree it.
I think FPGA is focus on function. But ASIC pays its attention to the Timing and Area, even Power, Datapath, DFT. So after simulation we can finish the FPGA, but there are many steps for finishing the ASIC: Simulation, STA, Conformal, etc.
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