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need help on this comparator circuit

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sean415

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Hi, I came across this multi-stage comparator circuit. Is anybody familiar with this structure? What is the purpose of the cross-coupled nmos load (M3, M4) under the diff pair? Also, what is the purpose of M6~M11? What is the advantage of this structure?

Thanks!
 

what my understanding says:

in common mode as m3,m4 will act as diodes.
so gain of this stage will be lesser.
assume I1 current is in each branch of pair.
after keeping m6 and m7 some of current will be passed through m6,m7
current through m3,m4 will decrease so Gm of m3,m4 will decrease.
as gain is inverse proptional to Gm of M3,M4 so overall gain of first stage will improve.
second stage will further enhance this and due to cross coupled pair on top you will get see better frequency response for circuit
 

the function of M3，M4 is hysteresis.
you maybe have to read chapter8 of Allen book (CMOS_Analog_Circuit_Design_2nd)
 

also there is a positive feedback loop in M3 and M4, speed up the comparison.
 

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