Ramya Narayanaswamy
Newbie level 1
Hi,
I am using Synopsys toolchain: both front end and back-end with UPF for low power specification. I am currently using 90nm library with the library having special cells for low power design. The library cells have power ground pins specified. Special cells like always-on and switch have internal_power and backup_power pins besides the default primary_power. Some of my logic is synthesized to always-on blocks implicitly. While I do back-end design, I get an error about missing power connections to these backup and internal_power. I am not sure of how to include the power connectivity of back_up and internal_power in UPF. The primary power and ground net connects are working good in UPF. Kindly help me in solving this issue.
Regards,
Ramya
I am using Synopsys toolchain: both front end and back-end with UPF for low power specification. I am currently using 90nm library with the library having special cells for low power design. The library cells have power ground pins specified. Special cells like always-on and switch have internal_power and backup_power pins besides the default primary_power. Some of my logic is synthesized to always-on blocks implicitly. While I do back-end design, I get an error about missing power connections to these backup and internal_power. I am not sure of how to include the power connectivity of back_up and internal_power in UPF. The primary power and ground net connects are working good in UPF. Kindly help me in solving this issue.
Regards,
Ramya