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    Translate MATLAB codes to Verilog Modules

    Hello
    Im new here. Im working on SPIHT Algorithm for my MS Thesis. Can someone please advise me on how i can convert MATLAB code to Verilog modules? I have some experience with Xilinx. Please help me

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    Translate MATLAB codes to Verilog Modules

    There are many ways to go about doing this. If you used the Xilinx system generator tools in Matlab, you should be able to simply output the HDL. Otherwise, there are other "C to H" style tools available. Here is an EE times article that talks about some of the latest advances
    http://www.eetimes.com/showArticle.j...cleID=49400117

    If you have decent Verilog experience, translating by hand will probably get you the most efficient results.


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    Re: Translate MATLAB codes to Verilog Modules

    Thanks alot mux_master

    Yes you are right that writing by hand will be most efficient. Ill try the Xilinx system generator though.
    Ill specify a bit about my thesis. See i am using a MATLAB code for SPIHT algorithm for image compression and I need to convert it as it is to Verilog and then make changes to optimize it. The SPIHT proceeds in several phases so i have individual MATLAB files for each function and i considered translating each file to individual modules of Verilog. Do u think this will work?
    Perhaps you could advise me further.

    Btw thanks alot for the article.



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    Translate MATLAB codes to Verilog Modules

    Yes, that is one way to go about doing it. The way I have done things like this in the past is to use the Matlab model to produce known inputs to stimulate the Verilog design. Then you can simulate the verilog design, collect the outputs and compare them to the Matlab outputs. Given the same inputs, the two systems should produce the same outputs. I have done this for delta sigma modulators and H.264 converter with good success.

    I am not too familiar with the SPHIT algorithm, but the general approach is to think about how the various sections of the algorithm can be divided into hardware modules and split it up that way. Making block diagrams for data flow is usually a good start. The individual files for each function may already provide a good logical partition as well.



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    Re: Translate MATLAB codes to Verilog Modules

    Quote Originally Posted by mux_master
    Yes, that is one way to go about doing it. The way I have done things like this in the past is to use the Matlab model to produce known inputs to stimulate the Verilog design. Then you can simulate the verilog design, collect the outputs and compare them to the Matlab outputs. Given the same inputs, the two systems should produce the same outputs. I have done this for delta sigma modulators and H.264 converter with good success.

    I am not too familiar with the SPHIT algorithm, but the general approach is to think about how the various sections of the algorithm can be divided into hardware modules and split it up that way. Making block diagrams for data flow is usually a good start. The individual files for each function may already provide a good logical partition as well.
    What you're saying sounds more of a verification, you're independently comparing output results of MATLAB to Verilog simulation result!!

    How exactly are you converting MATLAB code to Verilog is still a mystery to me.

    Correct me if I'm wrong here.



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    Re: Translate MATLAB codes to Verilog Modules

    You are correct ... I am talking about how to verify that once you do the conversion it is correct. I'm not sure how complex the algorithm in question is, but I would at least investigate doing it by hand. As for the method to do that, I don't think I can really say a step by step approach. Software implementation and hardware implementation are going to take different forms and this is going to be highly dependent on the nature of the algorithm.



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