harish_sharma1988
Newbie level 5
Hi
i want to design a ldo with the following specifications(which were already given in the specification sheet)
SPEC:
Parameter Value
Input Voltage 1.8 V(±10% Variation)
Output Voltage 1.2 V
Load Current 120mA
Quiescent Current 60µA
Transient response settling time 2µs
PSRR 40 dB (at 10 KHz)
Temperature -40ºC to 120ºC
Noise Spec 40µV / Hz
Load Regulation(R0=48 mΩ) ±0.004% / mA
Line Regulation 60 dB
so here the qstn is about the o/p load current which is 120mA. (I think this is a large value.) In order to meet the specification i have chosen a large W/L values for pmos pass element. So i got around 135 fingers. So when iam trying to draw the layout error amplifier(which is nmos differential pair with pmos current mirror load) is too small compared to pmos so it is not visible in the layout. So the qstn is about is that right to do so. Somebody please help me out.
I have used 180nm technology
i want to design a ldo with the following specifications(which were already given in the specification sheet)
SPEC:
Parameter Value
Input Voltage 1.8 V(±10% Variation)
Output Voltage 1.2 V
Load Current 120mA
Quiescent Current 60µA
Transient response settling time 2µs
PSRR 40 dB (at 10 KHz)
Temperature -40ºC to 120ºC
Noise Spec 40µV / Hz
Load Regulation(R0=48 mΩ) ±0.004% / mA
Line Regulation 60 dB
so here the qstn is about the o/p load current which is 120mA. (I think this is a large value.) In order to meet the specification i have chosen a large W/L values for pmos pass element. So i got around 135 fingers. So when iam trying to draw the layout error amplifier(which is nmos differential pair with pmos current mirror load) is too small compared to pmos so it is not visible in the layout. So the qstn is about is that right to do so. Somebody please help me out.
I have used 180nm technology