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low drop out voltage regulator

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harish_sharma1988

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Hi
i want to design a ldo with the following specifications(which were already given in the specification sheet)

SPEC:

Parameter Value
Input Voltage 1.8 V(±10% Variation)
Output Voltage 1.2 V
Load Current 120mA
Quiescent Current 60µA
Transient response settling time 2µs
PSRR 40 dB (at 10 KHz)
Temperature -40ºC to 120ºC
Noise Spec 40µV / Hz
Load Regulation(R0=48 mΩ) ±0.004% / mA
Line Regulation 60 dB


so here the qstn is about the o/p load current which is 120mA. (I think this is a large value.) In order to meet the specification i have chosen a large W/L values for pmos pass element. So i got around 135 fingers. So when iam trying to draw the layout error amplifier(which is nmos differential pair with pmos current mirror load) is too small compared to pmos so it is not visible in the layout. So the qstn is about is that right to do so. Somebody please help me out.
I have used 180nm technology
 

And whats exactly the problem with the driver using more area then the
amplifier ? Sometimes it simply comes out that way. Don't be shy, just do
the layout. I know, it looks weird, but it's totally ok, as long as you meet your
spec, also in an RC-extracted simulation. For such a big driver it might be a
good idea to connect the driver from both sides to get the gate resistance
down a bit.

If you have some more degrees of freedom you could try to switch to a boosted
n-Fet driver. That however requires the amplifier to run at higher supply which
seems not to fit to your spec

Best Regards

Andi
 
Hi
In this design i have used 3uF filter capacitance and 500pF output capacitance.
But i came to know that 50pF to 100pF (in extreme cases 200pF) is used not more than that as o/p capacitance. So my question is now about the value i have kept for o/p capacitance(500pF).........is dat ok.

and filter capacitor is 3uF (i think it should be large enough to block the regulations in the output) so with this large filter capacitance am i able to draw the layout.

Here iam attaching the ldo schematic please kindly go through this
 

Looks ok to me, beside maybe the the input pair could use
some resizing for lower offset ;) It seems that your input pair
is close to moderate/stron inversion which is ok for high bandwidth
differential pairs. However you could place it in weak inversion for
lowest offset.
Is the cap at the output mainly used for compensation or does it
work as a load model ? If it's load, theres not much you can do
If it's used for compensation you could try to trade between R and
C or use some different compensation scheme

However, if your circuit meets the specs, electrical and physical (area)
don't bother and go on. If you need the cap, you need it.

I almost forgot ... the 1u of the p-Fet driver is the length right ?
Why don't you reduce the devicelength a bit ? (if reliability vds is still ok)
Thereby you could reduce width as well and reduce the cap-load for
the input stage, therefore you save area, gain speed and maybe
you could also reduce the output cap cause usually the output driver
has a significant impact on the stability. Less cap here usually shifts the
output pole and improves stability ...

Best Regards

Andi
 

Add a unit size (1V) vac source in series to your vdd source and run an AC (or XF) analysis over your required frequency range. Plot the output's AC voltage in dB units - this is your PSRR.
 
Hi
In this design i have used 3uF filter capacitance and 500pF output capacitance.
But i came to know that 50pF to 100pF (in extreme cases 200pF) is used not more than that as o/p capacitance. So my question is now about the value i have kept for o/p capacitance(500pF).........is dat ok.

and filter capacitor is 3uF (i think it should be large enough to block the regulations in the output) so with this large filter capacitance am i able to draw the layout.

Here iam attaching the ldo schematic please kindly go through this

The explanation below the qstn was not understood so can u please elaborate it.


Thanks and Regards.,
 

Your PSRR response does not really look like a PSRR response at all.
Looks more like a loop gain curve ... Are you sure you followed erikl's
instruction ? Add an AC value of 1V to your supply and run an AC
simulation just as erikl proposed.
Maybe one addition to that. AC is always small-signal so for large signals
on the supply you don't get an idea whats going on. I had one case where
AC PSRR simulation was fine (-40dB at low frequencies and -20dB for 400Mhz
as a total max value) However the hardware came back and we had a
problem around 70Mhz due to package resonances. AC simulations didn't
show a problem at all, but transient simulations did ... ate up a giant amount
of time ... So sometimes it's a good idea to give some transients of different
frequencies on the supply and watch the output. If you get large peak to peak
noise it's a good idea to fire up some transient runs ;)

Best Regards

Andi
 

Just search for middlebrook's method. Connect a very big inductor from the feedback node back to your opamp input (its a dc short and ac open circuit) . add an ac voltage source to your input 1 v AC and run ac analysis by sweeping the frequency. observe the gain and phase plots and let me know.


Thanks
Am
 

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