bala_EE
Junior Member level 3
I have a question regarding the .sdf (standard delay format) generated after the synthesis step.
The file contains the input slopes and output loads of the gates used in the design.
The output loads specify the load that it is driving.
But what do the input slopes actually mean?
Also can anybody say how static timing analysis (STA) is done?
The file contains the input slopes and output loads of the gates used in the design.
The output loads specify the load that it is driving.
But what do the input slopes actually mean?
Also can anybody say how static timing analysis (STA) is done?