ieee
Member level 4
matlab +vhdl
The DSP Builder library SignalCompiler block reads Simulink model files (.mdl) and writes out VHDL files and Tcl scripts for hardware implementation and simulation. This HDL design can then be synthesized for implementation in Altera APEX II, APEX E, FLEX 10K, FLEX 6000, and Mercury device families.
https://www.mathworks.com/products/connections/product_main.shtml?prod_id=368
The DSP Builder library SignalCompiler block reads Simulink model files (.mdl) and writes out VHDL files and Tcl scripts for hardware implementation and simulation. This HDL design can then be synthesized for implementation in Altera APEX II, APEX E, FLEX 10K, FLEX 6000, and Mercury device families.
https://www.mathworks.com/products/connections/product_main.shtml?prod_id=368