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reset problem - could you help me please?

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always84

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reset problem

Hy, in my verilog module i need to initialize a group of variabiles only one time at the beginnin of the execution and i want to use reset signal to start the initialization. is it possible to make a initial block with an if condition when i've, in the same module, always blocks where the sesitivity list has reset as signal? I can't make an always block because i don't want to lose my data when reset is high during the execution.
 

Initial blocks are not synthesizable because they assign an initial state that cannot be guaranteed in real hardware upon power-up.
always84 said:
I can't make an always block because i don't want to lose my data when reset is high during the execution.
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The meaning of reset is stopping your execution.. It doesn't make any sense..
You will need this reset condition or not?
After power-up, reset signal can be used for initialization and after that you may not assert it again and you can go on your execution...
 

as the above said...
initials are not synthesizable and how you will lose data due to reset... reset is made just once active and than it is not active it never effect data just put all memory element or say reg to some initial condition to set reg to some particular value that comes from input genealogy load or pre-set signals are used...

dear frnd before putting hands on any HDL just refer digital circuits clearly it will help you a lot in writing codes with HDL...

hope you will follow my advise...
 

thanks for the answers. I know the use of reset but i think that my question wasn't correct...when the reset is hight at the beginning I initalize my vectors and matrixs, than i have always blocks that rapresents a state machine that use reset signal, than when the execution start I want to initilize my matrixs and the I want that the execution flow of the state machine goes using the reset too. My intention of using reset isn't the usual manner, I think. my module isn't syntetizable, it have to generate trafic for a integrated network.
 

It looks like you need two different reset signals. The first reset signal is the global reset signal that will cause the initialization of your memory structure. The other reset signal should control the state machine. Asserting this reset will put the state machine in the reset state, but not affect your memory structure.
 

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