davorin
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Benchmark synthesys?
How can I tell from a VHDL source if it is targeted for a chip or benchmarking?
Quartus gives me:
"Error: Design was synthesized in a benchmarking mode. No programming file will be generated."
And "help" isn´t helpful to me (o;
"ACTION: In order to generate programming files, you must modify the design so that Analysis & Synthesis can be performed successfully. Refer to previous synthesis messages for further information. "
So what to modify? (o;
How can I tell from a VHDL source if it is targeted for a chip or benchmarking?
Quartus gives me:
"Error: Design was synthesized in a benchmarking mode. No programming file will be generated."
And "help" isn´t helpful to me (o;
"ACTION: In order to generate programming files, you must modify the design so that Analysis & Synthesis can be performed successfully. Refer to previous synthesis messages for further information. "
So what to modify? (o;
