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spice code generation from cadence

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akhilmukund

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I have been working on a 16 bit DAC. Since the hardware is too big and more cycle times at the input, the simulation is taking a longer time(more than 5 days with pentium 4 processor and 4 GB Ram). Is it possible to generate Hspice code from the Cadence Virtuso schematic and simulate it from the HSPICE tool of synopsys.

Please suggest some methods to make my simulation faster.

akhil
 

akhilmukund said:
Is it possible to generate Hspice code from the Cadence Virtuso schematic and simulate it from the HSPICE tool of synopsys.
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If you have an Hspice license within C@dence Virtuoso you can of course generate an Hspice netlist from the schematic. But I doubt it will run faster than on the Spectre simulator.
With some editing, you could also convert a Spectre netlist into an Hspice one.
 

I don't use Cadence but normally when I design DACs & ADCs I try to check the circuit with partial circuitry for speed. When simulating the full circuit it can be useful to limit the nodes you save values from to prevent the disk speed being the limiting factor (with a 16 bit DAC you could have rather a lot of nodes depending on the design).

Keith.
 

You could also try to model things that are not critical to
bandwidth or accuracy, more simply. Like, the front end logic
probably could be verilog or veriloga. And of course for top
level type simulations the whole DAC could be behavioral
most likely.

Knowing when to fight, and when to fake it, is key.
 

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