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  1. #1
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    qpsk neural net equalizer

    I did my graduate thesis about Neural Networks Embedded FPGA. Do anyone want to share docs about it? I used Matlab and Verilog HDL to design my Equalizer....

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    fpga neural networks

    hai mine is naresh ..now i am entering into final year of my graduation..i want to do thesis in Neural Networks Equalizer Embedded FPGA so give me some suggestions



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    equalizer in fpga

    Hi, so.....what exactly is "Neural Networks Equalizer Embedded FPGA" ?
    :D



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    Re: Neural Networks Equalizer Embedded FPGA

    I understand Neural Networks as I have personally done some work on them, but what about the Equalizer? Do you mean a Neural Network Processor that after training can be used for some sort of Equalization (e.g. QPSK Channel Equalization)?



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    Re: qpsk neural net equalizer

    Hi, I've started to work on implementing neural network in fpga. please help me and guide me. Could you share your design files if possible?
    You can send me those to my e-mail bhkim91 at yahoo dot com.

    Thanks.

    Byung

    Quote Originally Posted by ThaiHoa
    I did my graduate thesis about Neural Networks Embedded FPGA. Do anyone want to share docs about it? I used Matlab and Verilog HDL to design my Equalizer....



  6. #6
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    Re: Neural Networks Equalizer Embedded FPGA

    No we cannot give you the code! This is out of the question, I hope you understand this! Instead, we can help you if you get stuck along the process of coding, simulation, etc.



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  7. #7
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    Re: Neural Networks Equalizer Embedded FPGA

    Quote Originally Posted by FuzzySNR View Post
    No we cannot give you the code! This is out of the question, I hope you understand this! Instead, we can help you if you get stuck along the process of coding, simulation, etc.
    How do one implement the sigmoid function using Verilog? I have read about piecewise linear approximation and look up tables .. but how do I fill these LUTs or index them?

    secondly, matlab normalizes the input to (-1,1) range, I changed that to (0,100) and discarded the fixed point part to ease HW implementation, I will do the same to the weights, How will this affect the implementation in FPGA?



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