DRV CHECKS max tran, max cap and max fanout ?

DRV CHECKS

In DRV checks we check for max tran, max cap and max fanout..

what are these values for? or why are these required?

whats the difference between max cap and max fanout?

Please help me in this query....


thanks

any answer please

are you referring to max_tran, max_cap and max_fanout in synopsys liberty timing files?

please any body genius enough to answer these queries?


atleast to upload the docs related to this......

still waiting for reply...............................

what is max trans, max cap and max fanout violation?

if we met the timing constraints and stiil have max trans violation, then should we reduce the max trans or should we leave this as it is because it is not giving any violation.

I am amazed!

not even a single reply???????????????????

so far I know

max_cap and max_tran are the design manufacturable rules

At any cost your design has to satisfy and meet that rules

These are mentioned in the sdc file

If you have not mentioned those constraints explicitly , fab internally has some rules accordingly the max_cap and max_tran values are taken into account.

If you specified those constraints explicitly then that value should be less than the implicit design rule value then only your constrained value taken into account and your value is being over ride the implicit design rules. else what ever value there previously remained as it is.

If you need more information download synopsys user guide

max_tran: is a parameter set so your synthesis tool knows how big or small the driver cells need to be.for example if you lower max_tran numbers, then, synopsys will pick larger cells in order to improve signal rise/fall times or visa-versa. Its a balancing act between design size and speed of signals in the design.

max_cap: is another parameter you set to tell the synthesis tool how much wire capacitance is allowd on the wires before a driving cell upsizing is to be attempted.

max_fanout: is yet another parameter which tells the synthesis tool how many loads should be dangled on a driver. For example if you set it to 6, then, six standard loads are allowed on each driver.

Don't think of these parameters as discrete. Use them together to control the synthesis tool.

if you read your liberty file, you will see each time table have for index, the transition and capacitance.

So if a violation occurs in transition or capacitance, that's indicate the value is outside this table and then the tool needs to extrapolate to calculate the new timing value. But by extrapolating, you don't know how false you are?

If the violation is small, the tool can make a small error during the extrapolation but in the others case, you don't know and it's better to fix them.

dont know what the hell you are saying but if i understand you your explanation has nothing to do with the question.

Sorry rakko, do you reply for me?

the DRV checks, is as mention as the first post from jitendravlsi, they want to know if he needs to fix them or not.

I just indicate the max_trans & max_cap are define by the liberty file. You could also change this value in the synthesis tool, but the tool will take the worst value.

And I try to explain why this violation need to be fixe. Because the time table inside the liberty file have as index the capacitance and the transition, and if your design violated the max trans/cap rules, the tool needs to extrapolate to obtain a timing value.
And if the transition is very far from the last table index, you don't know if the extrapolated value is correct or not (versus the reality).

And my explanation is completly related to the question, sorry for you.

best regards.