raghava
Member level 2
HI all,
Can anybody help me to convert this verilog code snippet into VHDL using procedure. Where i_clk and i_reset are global. This logic meant to generate an asynchronoud reset.
task ApplyReset;
begin
@ (negedge i_clk); i_reset = 1'b1;
@ (negedge i_clk);
@ (negedge i_clk);
@ (negedge i_clk); i_reset = 1'b0;
end
endtask
I conveted like follow.
procedure ApplyReset is
begin
wait until i_clk'event and i_clk = '0' ; i_reset <= '1';
wait until i_clk'event and i_clk = '0'; i_reset <= '0';
end ApplyReset;
Its fiving syntax error at procedure.
I appreciate your help.
Regards
Can anybody help me to convert this verilog code snippet into VHDL using procedure. Where i_clk and i_reset are global. This logic meant to generate an asynchronoud reset.
task ApplyReset;
begin
@ (negedge i_clk); i_reset = 1'b1;
@ (negedge i_clk);
@ (negedge i_clk);
@ (negedge i_clk); i_reset = 1'b0;
end
endtask
I conveted like follow.
procedure ApplyReset is
begin
wait until i_clk'event and i_clk = '0' ; i_reset <= '1';
wait until i_clk'event and i_clk = '0'; i_reset <= '0';
end ApplyReset;
Its fiving syntax error at procedure.
I appreciate your help.
Regards