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**broken link removed**
Date : January 28, 2010
Time : 9.30 AM – 10:30 AM India Standard Time
Date : January 28, 2010
Time : 3:00 pm - 4:00 pm Central European Time
Date : January 28, 2010
Time : 9:00 am - 10:00 am Pacific Standard Time (USA)
See: **broken link removed** or:
http://www.aldec.com/Events
Presenters :
CVC (Contemporary Verification Consultants Private Limited) - Srinivasan Venkataramanan (Srini), Chief Technology Officer
AldecŸ - Jaroslaw (Jerry) Kaczynski – Aldec, Inc. Technical Marketing Engineer
Abstract :
Modern digital designs have to transfer large amount of data across various blocks/IPs, especially in the SoC arena. Traditional solutions using scalar or vector variables are too simplistic and do not allow efficient managing of data. Also they can’t enforce directionality among vector fields, can’t capture transfer protocol restrictions, compliance metrics, etc. Fortunately, SystemVerilog introduced a new construct called 'interface' that wraps data structures, transfer directions, protocol monitors in terms of assertions, cover properties and also compliance metrics via cover groups. The SystemVerilog interface also supports methods of processing the data for TLM style modeling, bandwidth measurement, etc. all into one, convenient, new design entity. SystemVerilog interfaces quickly found their way into new designs, as they are useful for both RTL designers and verification engineers. This webinar explains typical elements of SystemVerilog interfaces and introduces basic concepts of using them in your designs and testbenches.
Agenda :
Introduction
Deficiencies of traditional variables
Simple interfaces
Modports
Assertions inside interfaces
Capturing compliance metrics within interfaces
Virtual interfaces
Typical applications of interfaces
Are interfaces synthesizable?
Conclusion and Q&A
View All Aldec Events: http://www.aldec.com/Events
We hope you and your colleagues will attend.
Thank you.
CVC Team &
The Marketing Communications Team
Aldec, Inc.
Date : January 28, 2010
Time : 9.30 AM – 10:30 AM India Standard Time
Date : January 28, 2010
Time : 3:00 pm - 4:00 pm Central European Time
Date : January 28, 2010
Time : 9:00 am - 10:00 am Pacific Standard Time (USA)
See: **broken link removed** or:
http://www.aldec.com/Events
Presenters :
CVC (Contemporary Verification Consultants Private Limited) - Srinivasan Venkataramanan (Srini), Chief Technology Officer
AldecŸ - Jaroslaw (Jerry) Kaczynski – Aldec, Inc. Technical Marketing Engineer
Abstract :
Modern digital designs have to transfer large amount of data across various blocks/IPs, especially in the SoC arena. Traditional solutions using scalar or vector variables are too simplistic and do not allow efficient managing of data. Also they can’t enforce directionality among vector fields, can’t capture transfer protocol restrictions, compliance metrics, etc. Fortunately, SystemVerilog introduced a new construct called 'interface' that wraps data structures, transfer directions, protocol monitors in terms of assertions, cover properties and also compliance metrics via cover groups. The SystemVerilog interface also supports methods of processing the data for TLM style modeling, bandwidth measurement, etc. all into one, convenient, new design entity. SystemVerilog interfaces quickly found their way into new designs, as they are useful for both RTL designers and verification engineers. This webinar explains typical elements of SystemVerilog interfaces and introduces basic concepts of using them in your designs and testbenches.
Agenda :
Introduction
Deficiencies of traditional variables
Simple interfaces
Modports
Assertions inside interfaces
Capturing compliance metrics within interfaces
Virtual interfaces
Typical applications of interfaces
Are interfaces synthesizable?
Conclusion and Q&A
View All Aldec Events: http://www.aldec.com/Events
We hope you and your colleagues will attend.
Thank you.
CVC Team &
The Marketing Communications Team
Aldec, Inc.
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