Cell mapping for device parasitic extraction not found

Hi everybody!

My question is regarding a particular error I get while running PEX on my layout using Cadence & Calibre. I have passed all DRC tests, and even LVS. Currently, when I run PEX, all the components in my layout are ignored due to the following errors:

ERROR: Could not find cell mapping for device spiral_s2_std. Ignoring instance g.
ERROR: Could not find cell mapping for device mimcap_2p0_wos. Ignoring instance 0.
ERROR: Could not find cell mapping for device nmos_rf. Ignoring instance 2.

These errors repeat themselves for every nmos, mim capacitor, and inductor that are part of my layout. I was considering that these errors might be due to an hcell/xcell related problem, but I have tried formatting the data in the hcell/xcell file many different ways, even referring to threads like these, but to no avail.

If someone has any ideas or suggestions on how I might go about fixing this problem, it would be greatly appreciated!

Thanks for your time!

Added after 4 hours:

Mediocre success with befuddling reasons!

Turns out the schematic netlist that was being used had an X at the beginning of every component description line. I added an extra X to every line that already had one X, and somehow I received 0 errors. It then asked me to set the connection pins, with an option of doing it automatically. I picked for it to perform that automatically.

After the connection pins were set, I ran PEX again, and this time there were no errors. I removed the additional X's that I had added earlier, and ran PEX. Again, there were no errors reported.

In the hcell/xcell file, I have followed a slightly different format, which is as follows:
layout_cell_name* model_cell_name

I'm not sure if the * makes a huge difference, but I think that might be a placeholder for the naming convention of the various components, ex. ind_std_01 for a generic component ind_std.

Finally, out of curiosity, I checked the output file from the PEX process and there are some parasitic components in there!

Not entirely sure if the whole process worked fully yet, since this is just my first layout ever. I'll assess the output, tweak the settings, and post my final results later.

I've been trying to fiddle with the settings on and off for several days now and I am still not able to extract parasitic RC networks and coupling capacitors from my layout. All I can get as an output is a list of identical inductors, capacitors, and transistors in the calibre view. The netlist that the PEX routine generates does not specify any parasitics in the circuit either.

If anyone has any suggestions or ideas I could try to fix the problem, it would be much appreciated.

Hello,
I have the same question.
After some try, I extract successfully my schematic, but I am not sure my solution. Here is my process:
At beginning I have exactly the same problem: with output netlist “calibreview, schematic”. The files ‘calview.cellmap’ is like:
(cell
(lib cell ivpcell)
(
(B B)
(D D)
(G G)
(S S)
)
)
Then I try output netlist “ELDO”, and modifier the ‘calview.cellmap’ to change the name of connection pins. It work.
After that, I retry the “calibreview, schematic”, and modifier the connection pins in ‘calview.cellmap’, now it’s like:
(cell
(lib cell ivpcell)
(
(b B)
(d D)
(g G)
(s S)
)
)
It works!!!
So, in my opinion, the problems most come from the connection pins in file ‘calview.cellmap’. A little suggestion maybe not necessary, restart your calibre or cadence to try new calview.cellmap.
Good luck. And if you have more ideas, please tell me. Thank you.