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actel against Xilinx competition

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joanna_seczkowska

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I run the same project once on spartan 3 and then on proasic (actel)
On Xilinx design evironment I received 94.5 MHz estimated frequency (by usuing LUT's).
On Actel design environment (by using RAM) I got 16MHz estimated frequency

Does anyone know what should be considered (in project optimization) when moving from Xilinx to Proasic?
 

I think the difference is rather big to judge on the components themselves. You should really investigate the worst case path in the Actel case.

Did you apply the correct optimisation settings? Did you give the tools the correct target clock frequency?
 

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