joanna_seczkowska
Newbie level 6
I run the same project once on spartan 3 and then on proasic (actel)
On Xilinx design evironment I received 94.5 MHz estimated frequency (by usuing LUT's).
On Actel design environment (by using RAM) I got 16MHz estimated frequency
Does anyone know what should be considered (in project optimization) when moving from Xilinx to Proasic?
On Xilinx design evironment I received 94.5 MHz estimated frequency (by usuing LUT's).
On Actel design environment (by using RAM) I got 16MHz estimated frequency
Does anyone know what should be considered (in project optimization) when moving from Xilinx to Proasic?