Gain Saturation in Common Source Amplifier

Hi,

I was designing a CMOS common source amplifier using tsmc018(level = 49) model MOS.

I was trying to increase the DC gain by reducing the overdrive of M1 and correspondingly increasing its W/L of M1 keeping the current constant at 20u.

W/L of M2 was constant throughout.

But the gain became constant (~68.8 ) below 140mV Overdrive. Can somebody explain why the gain saturated?

I have attached the schematic.

Thanks in advance

Hi rage
How can I open your schematic? I mena in which software? As you keep increasing W/L keeping Id constant after a certain time the transistor goes into sub-threshold region of operation. This is the point where you can get the maximum gain from the transistor for a given current. Since now the transistor transfer function is exponential similar to the bipolar transistor and so the gm becomes a function like Ic/Vt where Vt is the thermal voltage. So W/L does not have any effect now. If you want to increase the gm further it is necessary to increase the current.
Hope that explains it.

@aryajur

Thanks for replying.

Kindly correct me if I am wrong. To enter into subthreshold region the Vgs of the MOS should be less then threshold voltage but as I said the gain became constant below 150mV overdrive.

So the MOS should not have entered subthreshold region.

I am using "Micro cap". I have attached a spice file of the same.

Thanks

Hi rage,
The netlist output for the MOS transistors is coming out with Source and Drain terminals swapped. It should not matter since low voltage MOS are symmetrical devices.
So from the netlist it seems you hold the gate voltage constant at 0.5V and plot the AC gain. Then I assume you are changing the size of M1 and resimulating and checking the gain change and after sometime you see the gain saturate. Did I understand correctly?

Can you check if M1 is going into triode? Because if the gate voltage of M1 is not set correctly based on the size of M1 either M2 or M1 would go into triode, that should show up as a gain decrease. But you say the gain isn't decreasing just saturating?

aryajur said:

Hi rage,
The netlist output for the MOS transistors is coming out with Source and Drain terminals swapped. It should not matter since low voltage MOS are symmetrical devices.
So from the netlist it seems you hold the gate voltage constant at 0.5V and plot the AC gain. Then I assume you are changing the size of M1 and resimulating and checking the gain change and after sometime you see the gain saturate. Did I understand correctly?

Can you check if M1 is going into triode? Because if the gate voltage of M1 is not set correctly based on the size of M1 either M2 or M1 would go into triode, that should show up as a gain decrease. But you say the gain isn't decreasing just saturating?

Click to expand...

I am holding the drain current constant by varying both gate voltage and W/L of M1. And below 0.45 gate voltage(Vth = 0.3662743) the gain changes by very small amount(I checked it once again by flipping the device the gain is not constant. Sorry)

At VGS = 0.4 , W = 130u L =.36u, gain = 68.336
VGS = 0.45, W = 40u L =.36u, gain = 68.653

Both the transistors are in Saturation.

Hi rage,
I simulated the circuit you sent and I get the same results. THen analyzing this further I see that when the size is increased, the gm may be increasing but the output impedance of the transistor reduces as shown by the attached plot. This thing I think causing the gain saturation although I don't know what secondary effect is this.

But how does the o/p resistance depend upon the W/L of the Mosfet.

It should depend on LAMBDA and Id I suppose. Or is this a general first order approximation ?

And how did you plot the output resistance. I tried plotting VDS/Id but I am getting a different plot.

rage_speed said:

And how did you plot the output resistance. I tried plotting VDS/Id but I am getting a different plot.

Click to expand...

After sweeping VDS in DC simulation and plotting Id versus VDS and taking derivative of Ids you will get ΔIds/ΔVds which is the expression for 1/(output resistance).

It Looks like your output impedance falls due to substrate-current-induced body effect. Can you check if you have current leackage into you bulk?

the reason given by arajur (SUBTHRESHOLD GAIN SATURATION) is true. However, here we have to talk about WEAK INVERSION REGION, not subthreshold. However, the exponential equations hold in this region, so the gain is in the form ID/nVt where n is a parameter typical of the process, namely the "slope factor".
Hope i've cleared your ideas.

Hi rage,
This is turning to be an interesting discussion. I want to get the the root cause of this. There could be a couple of things which we should analyze:
1. Is the transistor reaching weak inversion and exponential behavior? I don't think this should be the case but just to rule out that I will plot the log of Ids vs vgs to see how that looks in the region we are operating.
2. Is this secondary affect due to changing the Gate voltage since the gate voltage would be influencing the channel and influences the output impedance normally.
3. We need to check the substrate current as monya suggested.

Ideally from the 1st order square law equation the gain should increase since ro should remain the same and gm is increasing, but obviously some suttle second order affect that is there in the transistor model but we are not looking at is affecting the result.

I will get back on this after more analysis today.

Hi rage,
So I checked all things. There is no Bulk current. The reason that the gain saturates is because the gm stops increasing at the rate it is supposed to. The reason for that is actually the transistor is going into sub-threshold.
To prove that, I plotted the log of Id vs Vgs. Attached is that graph for both transistor sizes that you use. From the plot we can see that your operating region for both transistor is in subthreshold.
I know from the VTH0 and Vgs values it doesn't add up. But the actual vth in a BSIM model is a very complicated function so from simulation we see that we enter subthreshold region and so the gain saturates.