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how to deburr NAND2 gate (graph enclosed)?

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urian

urian

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how to deburr

hi,there
I have drawn a nand2 gate.when i simulating it ,i found there are some burrs in the plot,do they cause some problem when i using them in a pipeline adc?how can i deburr these?
i'm using 90nm pdk
 

how to deburr

the problem arises only when they are deep enough to cross the threshold voltage of your gates.
You will always see in your logic signals due to switching of other logic gates (and it gets worse after pex).
 

from your simulation, it looks like they are small enough that you dont need to worry about them.

They are so small that its unlikely that they will effect any digital logic.
 

A lot of that is just edge feedthrough, nothing you can do
but play with the input risetimes (faster than necessary,
helps none).

Just be sure none of them are from simultaneous input
switching, which might baloon into larger transients with
environmentals or delay mismatch.
 

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