same FPGA design, but resourse usage is quite different!

synplify ¨cell usageentity

When i use altera and xilinx's fpga to design a multiplier, i find the resource usage is quite different. My synthesize tool is synplify pro 7.2.
The multiplier is 5 * 8 bit. Altera's consumes 74LUT, but Xilinx 35LUT.

why the same design, but quite different resource usage?


resource usage
altera fpga : acex10 74LUTs
xilinx fpga : spartan 2e 35LUTs



Design view:work.try_mult(arch)
Selecting part ep1k10tc100-1

Total LUTs: 74 of 576 (12%)
Logic resources: 74 LCs of 576 (12%)
Number of Nets: 135
Number of Inputs: 317
Register bits: 13
EABs: 0 (0% of 3)
I/O cells: 27




Resource Usage Report for try_mult
Mapping to part: xc2s50eft256-7
Cell usage:
FD 12 uses
FDR 1 use
GND 1 use
MULT_AND 24 uses
MUXCY 3 uses
MUXCY_L 31 uses
XORCY 31 uses

I/O primitives:
IBUF 13 uses
OBUF 13 uses
BUFGP 1 use
I/O Register bits: 13
Register bits not including I/Os: 0 (0%)
Global Clock Buffers: 1 of 4 (25%)
Mapping Summary:
Total LUTs: 35 (2%)









library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity try_mult is
Port ( clk : in std_logic;
ina : in std_logic_vector(8 downto 1);
inb : in std_logic_vector(5 downto 1);
y : out std_logic_vector(13 downto 1));
end try_mult;

architecture arch of try_mult is

signal temp : std_logic_vector(13 downto 1);
-------------------------------------------------------------------
begin
-------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
temp <= (ina) * (inb);
end if;
end process;
y <= temp;
----------------------------------------------------------------------------------
end arch;

the resource cost rely on the synthesis tools, implement tools and the fpgas' architecture.

As "ydao" said, But you can also see some similar things

1) Same number of flip flop = 13
13 register bit in Altera
12 FD + 1 FDR in xilinx
2) Same number of logic
Xilinx LUT contain 2 FF and 2 4-input LUT
Altera LUT contain 1 FF and 1 4-input LUT
3) Same number of I/O

Which device is suitable for you? For me, I love xilinx software.

ydao said:

the resource cost rely on the synthesis tools, implement tools and the fpgas' architecture.

Click to expand...

yes, you are right. but i use the same tool (synplify7.2) for altera and xilinx, it is not good enough?

elektrom said:

As "ydao" said, But you can also see some similar things

1) Same number of flip flop = 13
13 register bit in @ltera
12 FD + 1 FDR in xilinx
2) Same number of logic
Xilinx LUT contain 2 FF and 2 4-input LUT
@ltera LUT contain 1 FF and 1 4-input LUT
3) Same number of I/O

Which device is suitable for you? For me, I love xilinx software.

Click to expand...

no,no the LUT usage is not same.
for spartan2e, a CLB contains 2 slice, a slice constains 2 LUT, LUT is spartan2e's basic logic cell.

elektrom said:

Which device is suitable for you? For me, I love xilinx software.

Click to expand...

i use altera and xilinx for different project.
i had used altera's flex, apex, acex, and cyclone.
for xilinx, i use spartan, virtex-e now.

i love xilinx too.

Hi..

Ya, sure that you will have different LUT. it is not totally cause by the synthesizer. It because of resource built-in Altera FPGA and Xilinx FPGA. For Altera FPGA, the synthesizer will implement the Multiplier using only LUTs. But for Xilinx's Spartan 2e had a built-in core call "MULT_AND" which is an multiplier, so the synthesizer is smart enough to use this element built-in FPGA for multiplication. therefore by using this core, you won't be using LUT to create the multiplier.. Hence you will get more LUTs in Altera FPGA, while less LUTs in Xilinx FPGA. You can reference to the technical spec when u design both vendors's FPGA device... Hope this help