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Digital-PLL design issue with fractional-N counter

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talk2god

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Hi,
Can anyone help me out :?:

I am designing a Digital-PLL with a center freq. of 2.048Mhz with 100 Hz spacing. I have a 66Mhz crystal and to achieve this step-size, the count value for the fractional-N counter is too high. How do i overcome this difficulty :roll:
 

adpll main design difficulty

I am about to implement an vhdl ADPLL in the next weeks.

i found a good explanation about adplls at:
http://www.aicdesign.org/2003%20PLL%20Slides/L050-ADPLLs-2UP(9_1_03).pdf

example adpll code can be found at:
**broken link removed**

if you find out how good or bad the example implementation is let me know please.


regards
-hans
 

adpll

Zarling has very much devices for decide your problem.
 

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