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How to consider Synchronous DCDC buck converter output stage

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chudong

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Synchronous DCDC buck converter has output High side Power MOS and Low side Power Mos.
And how to consider the layout for the latch up and ESD safe?
 

Just respect all the PDK's ESD & latch-up rules:
  • extended s/d widths
  • (possibly partial) salicide blocking
  • double (p+ & n+) guard rings for each powerMOS
  • minimum distances
 

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