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    reduce resource utilization - aes fpga

    i hav vhdl code for aes encryption/decryption which runs fine during behavioral simulation. most parts of the algorithm are implemented using look up tables.


    the synthesis went on running................... after a day's wait it got synthesised, but slice LUTs were overutilized.

    similar to software, in hardware is there any means to free up and reuse some latches, once its initial function is done ?

    pl anybody reply

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    Re: reduce resource utilization - aes fpga

    Hi deepamj,

    First try to map your LUTs (AES SBOXes) to the FPGA RAMs it will reduce logic. If it will not help you can always optimize AES core.
    You can design 10, 20, 40 ... clock cycle core depends on your performance.

    Bests,
    Tiksan
    http://syswip.com



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    reduce resource utilization - aes fpga

    helo tiksan

    thank you for the reply.

    i'm newbie in fpga. can u elaborate what's meant by "mapping LUTs to RAMs" and 10,20,40....clk cycle core.
    .it will be helpful

    hopes for a reply



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    reduce resource utilization - aes fpga

    hats off to you tiksan for your blog and sharing verification ips



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    Re: reduce resource utilization - aes fpga

    I'm really happy if someone found my blog useful :D
    Thank you very much



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    reduce resource utilization - aes fpga

    deepa, you have to code sbox in such a way that RAM on FPGA gets inferred or instantiate RAM on FPGA and use it to program sbox. Here is one link that might be useful to start

    http://www.dilloneng.com/documents/howto/ram_inference

    google for inferring block ram fpga



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    Re: reduce resource utilization - aes fpga

    Hi deepamj,

    This is AES VHDL core form opencores.org. It can be useful for you.
    I didn't try it so can not tell anything about this design.

    Best Regards,
    Tiksan



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    Help in Behavioral simulation

    Quote Originally Posted by deepamj
    i hav vhdl code for aes encryption/decryption which runs fine during behavioral simulation. most parts of the algorithm are implemented using look up tables.


    the synthesis went on running................... after a day's wait it got synthesised, but slice LUTs were overutilized.

    similar to software, in hardware is there any means to free up and reuse some latches, once its initial function is done ?

    pl anybody reply
    Hi!
    i have implemented AES encrytption and decryption using verilog. I have simulated the result of encryption module, the problem that i am facing is in the simulation of Decryption module.How can i get the correct result?
    Thanks



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    Re: reduce resource utilization - aes fpga

    Quote Originally Posted by Syswip
    Hi deepamj,

    First try to map your LUTs (AES SBOXes) to the FPGA RAMs it will reduce logic. If it will not help you can always optimize AES core.
    You can design 10, 20, 40 ... clock cycle core depends on your performance.

    Bests,
    Tiksan
    http://syswip.com
    I'm trying to find a way to map my LUTs to RAM, but still I couldn't ..
    Tareq suggested to do so by inferring BRAM or DRAM .. but this is not a solution, because my logic is not initially a RAM .. I just want to MAP my logic to unused RAM blocks ..
    So, any help ? .. do u know how this can be done Syswip ?



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    Re: reduce resource utilization - aes fpga

    Are you talking about large LUTs, as utilized in the said AES core, or regular logic elements that are implemented as small 4 or 6-input LUTs in FPGA? The latter can't be effectively mapped to internal RAM, I fear.



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    Re: reduce resource utilization - aes fpga

    Quote Originally Posted by FvM
    Are you talking about large LUTs, as utilized in the said AES core, or regular logic elements that are implemented as small 4 or 6-input LUTs in FPGA? The latter can't be effectively mapped to internal RAM, I fear.
    I am talking about the LUTs in the following Synplify utilization report:


    Mapping to part: xc3sd1800afg676-4
    Cell usage:
    DSP48A 33 uses
    FDC 2615 uses
    FDCE 457 uses
    FDE 2 uses
    FDP 1 use
    FDPE 2 uses
    GND 14 uses
    MUXCY 22 uses
    MUXCY_L 1140 uses
    MUXF5 4336 uses
    MUXF6 603 uses
    MUXF7 2 uses
    VCC 13 uses
    XORCY 997 uses
    rcip_arctan_parallel 1 use
    rcip_vr_parallel 7 uses
    LUT1 156 uses
    LUT2 3016 uses
    LUT3 14157 uses
    LUT4 14004 uses


    SRL primitives:
    SRLC16E 2 uses
    SRL16E 1 use

    I/O Register bits: 0
    Register bits not including I/Os: 3077 (9%)

    DSP48s: 33 of 84 (39%)
    Total load per clock:
    clk_8mhz: 3090

    Mapping Summary:
    Total LUTs: 31336 (94%)



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