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Cmos inverter Design (Issue -output spike)

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Anand15

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Hi all,

I am designing a inverter in 0.25u tsmc tecnology.
when i am doing transient simulating i am gatting spike.
VDD=2.5V. spike around 0.1v.
even the DC characteristic is perfect.

Thanks & Regards
Anand
 

is this spike coming at trasition time
can you post picture of waveform zooming region of spike??
 

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Dear i am unable do atteched any file file or pics.
what I'll do.
 

are u not getting the way to upload pic/file or any different issue??
 

as a trial put some cap on output node and resimulate...
if spike decreases then its control system theory of under/over/crirital damping
 

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