Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

time skew including in hold/setup time problems

Status
Not open for further replies.

yamini1909

Newbie level 4
Joined
Dec 6, 2009
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
india
Activity points
1,311
time skew

how to include time skew in hold/setup time problems?
 

Re: time skew

Do you want to consider clock skew during synthesis?
If yes you only need to put skew to your clock and synthesis tool will include it during timing calculation.

Syswip,
http://syswip.com/
 

You can set the clock uncertainty for the clock to consider the skew issue
 

you can play with the set_clock_latency commands for playing with skew in the earlier stages (synthesis and placement).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top