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  1. #1
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    Co simulation of SystemC files with VHDL testbench

    Sorry if this is not the correct place to post my question,

    I am intrested in co-simulation of VHDL and systemC

    I want to use VHDL testbench in order to test systemC files

    The programs I am using for this are Questasim and Modelsim (of mentor graphics)

    Anyone has a good tutorial about this or can explain me how it is done ?



    Thanks in advance ,

    Dor

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  2. #2
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    Co simulation of SystemC files with VHDL testbench

    What is the simulator you are using? And what do you do with the DUT model?



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  3. #3
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    Re: Co simulation of SystemC files with VHDL testbench

    hello pini1 , I need to use modelsim with vhdl testbench which are given to me

    so writing systemC testbench is not an option. thanks anyway


    farhada , I am using modelsim as a simulator and I am not quite sure what you mean

    with DUT model.

    if you can please explain I will be grateful


    Dor



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  4. #4
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    Re: Co simulation of SystemC files with VHDL testbench

    Dor,
    Look at their manual, I found: VHDL Instantiating SystemC

    We have Verilog/SV-SystemC training examples @ CVC, can quickly make it to VHDL if needed. Contact me offline info@cvcblr.com if interested.

    Good luck
    Ajeetha, CVC
    www.cvcblr.com



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