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  1. #1
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    How to stop simulation in VHDL testbench?

    Hello,

    I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog?

    Regards,

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  2. #2
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    Re: How to stop simulation in VHDL testbench?

    Hi,

    You can write at the end of your testbench:

    assert false report "end of simulation" severity failure;


    Devas


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  3. #3
    Junior Member level 2
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    How to stop simulation in VHDL testbench?

    Hello Devas,

    Yes, the statement works!

    Thanks a lot!

    Regards,



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