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VHDL template to infer Xilinx Distributed RAM

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omara007

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Hi folks

Is there any VHDL template or coding guidelines suggested by Xilinx to infer its Distributed RAM the same way they suggest some other templates for Block RAM inference ?

P.S. I don't want to use CoreGen as I want to keep everything in my VHDL code.
My device is Spartan-3A DSP
 

You can get your anwer from XAPP464 or use the following teplate:

Code:
component RAM16X1S
-- pragma translate_off
generic (
-- RAM initialization (“0” by default) for functional simulation:
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
O : out std_logic
);
end component;

Hope it helps,

Best regards,
/Farhad
 

    omara007

    Points: 2
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