FIFO queue for storing the data

FIFO Design Doubts

Hi Experts,

I need to use the FIFO Design in my module for storing the data and retrieving back,The problem is My main module will read the data from the FIFO after my FIFO is full until it will become empty,up to my knowledge we can read and write the FIFO simultaneously,it is possible to design the FIFO that will be read and write different time and one of the main application of the FIFO is read and write at different clock frequencies.


Regards,
Kanimozhi.M

FIFO Design Doubts

I am not sure about what you want to do with your own FIFO system, so if my reply do not fit your need, just pass it .

If you want to read and write FIFO at different clock frequencies, just place read code and write code in 2 different sections that will be done at 2 different times.
For example, you use timer interrupt for increase a 32-bit integer variable each 1ms. In your main function, you can use this variable for doing 2 task at 2 different times.

Regards,

Re: FIFO Design Doubts

Hi,

I think you need not to have design FIFO, as most of the vendor have on chip FIFO/RAM blocks, just you need to use FIFO controller core available from your tool chain.

You can read and write FIFO from different clock the only thing you have to take care is control of fifo full , fifo empty signal at both side (fifo and processor side).

HTH
--
Shitansh Vaghela

Re: FIFO Design Doubts

what is fifo plz
can i get some hlp

Re: FIFO Design Doubts

sajal1975 said:

what is fifo plz
can i get some hlp

Click to expand...

Hi,

I hope following wave forms may help you to understand FIFO functionality.

Sample behavioral waveforms for design file Buf_FIFO.v

The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design Buf_FIFO.v. The design Buf_FIFO.v has a depth of 1024 words of 16 bits each. The output of the fifo is unregistered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.


The above waveform shows the behavior of the design under normal read and write conditions with aclr .



Below is another version of FIFO.

Sample behavioral waveforms for design file Buf_FIFO.v

The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design Buf_FIFO.v. The design Buf_FIFO.v has a depth of 512 words of 16 bits each. The output of the fifo is unregistered. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.


The above waveform shows the behavior of the design under normal read and write conditions with aclr .


HTH
--
Shitansh Vaghela